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VLSI – Verification Engineer

Pliops Israel (Ramat Gan) · Full-time · Experienced

About The Position

Highlights for this role:

  1. Develop ASIC verification environment for full chip, sub-cluster and unit levels
  2. Responsibility for generation and execution of verification plan for challenging digital blocks/chip
  3. Development of System Verilog, UVM based protocol/traffic generators, monitors, checkers and coverage
  4. Learn and work with great teammates 🙂 

Requirements

  • B.Sc. in Electrical Engineering from known university
  • Minimum of 3 years of experience in ASIC verification from semiconductor companies
  • Knowledge and experience in standard verification methodologies such as UVM/OVM
  • Demonstrated experience in building a complicated verification environment 
  • Knowledge in Formal verification and Emulation – Advantage
  • Knowledge in scripting languages such as Python or Perl – Advantage
  • Very good communication skills

Apply for this position