Physical Design Engineer
About The Position
Who We Are?
We are a growing startup company revolutionizing the Storage Processor world, with an ingenious solution. Founded in 2017 by industry leaders. We’re the cream of the crop, with a positive disposition, an optimistic vibe, and a can-do attitude.
We’re stronger together, at home and at work. Our mind is sharp and we’re quick on our toes, we lead by sharing, and empower by advising where to look but not what to see. Honestly, we're quite knowledgeable, however, we know there’s a lot more gray matter to color with learning.
Our Extreme Data Processor (XDP) is a hardware-based storage accelerator that enables cloud and enterprise customers to offload and accelerate data-intensive workloads using just a fraction of the computational load and power. It’s truly groundbreaking, you have to see it to believe it.
Pliops does not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity or expression, national origin, age, disability, veteran status, marital status, or based on an individual's status in any group or class protected by applicable federal, state or local law. Pliops encourages applications from minorities, women, the disabled, protected veterans and all other qualified applicants.
To find out more about us, click on the link below:
The role includes:
- Be part of a founding BackEnd team and tackle greatest technology challenges.
- Responsibility for RTL2GDS flow including Floorplan, Synthesis, Place and route, clock-tree, STA, signoff (Timing, DRC, LVS, EMIR)
- Take part in the definition of the Backend execution and methodologies.
- BSc. Degree in Electrical Engineering
- At least 5 years’ experience as BackEnd engineer from a leading semiconductor company at advanced process technology
- Hands-On experience in Macro level Implementation
- Hands on experience in physical design flows and methodologies: Synthesis , floor-planning, clock building and routing
- Hands on experience with signoff STA, LEC, DRC and EMIR
- TCL scripting and EDA tool flow
- Full-chip level Implementation - Advantage
- Power and Noise analysis – Advantage
- DFT knowledge – Advantage